The RA6T2 simulator is designed to simulate the behavior of the RA6T2 microcontroller. This document outlines the supported features and limitations of the simulator.
| Feature | Support Status |
|---|---|
| CPU | Support Partially |
| Operating Modes | Support Partially |
| Address Space | Support Partially |
| Resets | Support Partially |
| Option-Setting Memory | Support Partially |
| Low Voltage Detection (LVD) | Unsupport |
| Clock Generation Circuit | Support Partially |
| Clock Frequency Accuracy Measurement Circuit (CAC) | Unsupport |
| Low Power Modes | Unsupport |
| Register Write Protection | Unsupport |
| Interrupt Controller Unit (ICU) | Support Partially |
| Buses | Support Partially |
| Memory Protection Unit (MPU) | Support Partially |
| DMA Controller (DMAC) | Unsupport |
| Data Transfer Controller (DTC) | Unsupport |
| Event Link Controller (ELC) | Support Partially |
| IO Ports | Support Partially |
| Key Interrupt Function (KINT) | Unsupport |
| Port Output Enable for GPT (POEG) | Support Partially |
| General PWM Timer (GPT) | Support Partially |
| PWM Delay Generation Circuit (PDG) | Unsupport |
| Low Power Asynchronous General Purpose Timer (AGTW) | Support Partially |
| Watchdog Timer (WDT) | Unsupport |
| Independent Watchdog Timer (IWDT) | Support Partially |
| Serial Communications Interface (SCI) | Unsupport |
| I2C Bus Interface (IIC) | Unsupport |
| CANFD | Unsupport |
| CANFD ECC (CNECC) | Unsupport |
| Serial Peripheral Interface (SPI) | Unsupport |
| Cyclic Redundancy Check (CRC) | Unsupport |
| Trigonometric Function Unit (TFU) | Support Partially |
| IIR Filter Accelerator (IIRFA) | Unsupport |
| Boundary Scan | Unsupport |
| Secure Cryptographic Engine (SCE5) | Unsupport |
| 12-Bit A/D Converter (ADC) | Support Partially |
| 12-Bit D/A Converter (DAC12) | Unsupport |
| Temperature Sensor (TSN) | Unsupport |
| High-Speed Analog Comparator (ACMPHS) | Unsupport |
| Data Operation Circuit (DOC) | Unsupport |
| SRAM | Unsupport |
| Standby SRAM | Unsupport |
| Flash Memory | Unsupport |
| Internal Voltage Regulator | Unsupport |
| Security Features | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
|
Arm Cortex-M33 - Revision: r0p4-00rel1 - Armv8-M architecture profile - Single Precision Floating-Point Unit compliant with the ANSI/IEEE Std 754-2008 |
Support Partially |
- RA6T2 Simulator works as Arm Cortex-M33 Revision r0p3. - RA6T2 Simulator support Single Precision Floating-Point with FPv4. (Cortex-M33 supports with FPv5) |
| IDAU (Implementation Defined Attribution Unit) | Unsupport | The entire memory address space is always defined as Secure. |
| Memory Protection Unit (MPU) | Support | |
| SysTick timer | Support |
| Function | Support | Support Detail |
|---|---|---|
| Single-chip mode | Support | |
| SCI boot mode | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| Flash I/O registers | Unsupport | |
| Peripheral I/O registers | Support | |
| Standby SRAM | Support Partially | This area can be accessed, but the function of Standby SRAM is not supported. |
| SRAM0 | Support Partially | 0x2000_0000 - 0x2000_7FFF can be accessed, but the function of SRAM is not supported. |
| On-chip flash (data flash) | Unsupport | |
| On-chip flash (option-setting memory) | Support Partially | See "Option-Setting Memory". |
| On-chip flash (Factory Flash) | Unsupport | |
| On-chip flash (code flash) | Support |
| Function | Support | Support Detail |
|---|---|---|
| RES pin reset | Unsupport | |
| Power-on reset | Unsupport | |
| Independent watchdog timer reset | Support | |
| Watchdog timer reset | Unsupport | |
| Voltage monitor 0 reset | Unsupport | |
| Voltage monitor 1 reset | Unsupport | |
| Voltage monitor 2 reset | Unsupport | |
| SRAM parity error reset | Unsupport | |
| SRAM ECC error reset | Unsupport | |
| Bus master MPU error reset | Unsupport | |
| TrustZone error reset | Unsupport | |
| Cache Parity error reset | Unsupport | |
| Deep software standby reset | Unsupport | |
| Software reset | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| Block Protect Setting Register Select (BPS_SEL) | Unsupport | |
| Option Function Select Register 1 Select (OFS1_SEL) | Unsupport | |
| Permanent Block Protect Setting Register Secure (PBPS_SEC) | Unsupport | |
| Block Protect Setting Register Secure (BPS_SEC) | Unsupport | |
| Option Function Select Register 1 Secure (OFS1_SEC) | Unsupport | |
| Permanent Block Protect Setting Register (PBPS) | Unsupport | |
| Block Protect Setting Register (BPS) | Unsupport | |
| Option Function Select Register 1 (OFS1) | Support Partially | Only the function of HOCOEN and HOCOFRQ0[1:0] are supported in RA6T2 simulator. |
| Startup Area Setting Register (SAS) | Unsupport | |
| Option Function Select Register 0 (OFS0) | Support Partially | Only the function of IWDT is supported in RA6T2 simulator. The functions of WDT is not supported in RA6T2 simulator. |
| Function | Support | Support Detail |
|---|---|---|
|
Clock source: 1. MOSC, PLL. PLL2, HOCO, MOCO, LOCO, IWDTLOCO 2. TCK, SWCLK |
Support Partially | Only the clock of (1) is supported. |
|
Internal clock: 1. ICLK, PCLKA, PCLKB, PCLKC, PCLKD, GPTCLK, AGTLCLK, IWDTCLK, SYSTICCLK 2. FCLK, CANFDCLK, CANMCLK, IICCLK, SCISPICLK, CACMCLK, CACLCLK, CACMOCLK, CACHCLK, CACILCLK, JTAGTCK, SWCLK, TRCLK, TCLK, CLKOUT |
Support Partially | Only the clock of (1) is supported. |
| Security Attribute | Unsupport | |
| Oscillation Stabilization Time | Unsupport | |
| Oscillation Stop Detection Function | Unsupport | |
| Oscillation stabilization wait time for the main clock oscillator | Unsupport | |
| Main Clock Oscillator Drive Capability | Unsupport | |
| CLKOUT pin | Unsupport | |
| Trimming Control for LOCO, MOCO, HOCO | Unsupport | |
| Low power modes | Unsupport |
In simulator, clock source (HOCO, MOCO, LOCO, MOSC, PLL and PLL2) can not be stopped, and the related registers: HOCOCR, MOCOCR, LOCOCR, MOSCCR, PLLCR, PLL2CR also are unsupported. The clock frequency and clock source can be changed freely in simulator without stopping the current clock source.
| Function | Support | Support Detail |
|---|---|---|
|
Maskable interrupts 1. Peripheral function interrupts 2. External pin interrupts 3. Interrupt requests to CPU (NVIC) 4. DMAC control 5. DTC control |
Support Partially | (1)~(3) are supported. |
|
Nonmaskable interrupts 1. NMI pin interrupt 2. WDT underflow/refresh error 3. IWDT underflow/refresh error 4. Low voltage detection 1 5. Low voltage detection 2 6. RPEST 7. RECCST 8. TZFST 9. CPEST 10. Oscillation stop detection interrupt 11. Bus master MPU error |
Support Partially | Only (3) is supported. |
| Low power modes | Unsupport | |
| TrustZone Filter | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| BUS Masters | Support | |
| BUS Slaves | Support | |
| Arbitration | Unsupport | |
| Parallel Operation | Unsupport | |
|
Bus Error Monitoring Section - Illegal address access - Bus master MPU error - TrustZone Filter error - Bus error transmitted from each slave IP (in IPs) |
Unsupport | |
| Cache - C-cache on code bus - S-cache on system bus |
Unsupport |
| Function | Support | Support Detail |
|---|---|---|
|
Illegal memory access - Arm CPU has a default memory map. If the CPU makes an illegal access, an exception interrupt occurs. |
Unsupport | |
|
Memory protection 1. Arm MPU: Memory protection function for the CPU. 2. Bus master MPU: Memory protection function for DMAC/DTC. |
Support Partially | Only (1) is supported. |
| Function | Support | Support Detail |
|---|---|---|
|
Event link function - 215 types of event signals(includes software events) can be directly connected to modules. - The ELC generates the ELC event signal(includes software events), and software events that activate the DTC. |
Support Partially |
For source signal: Only the following event signal are supported: GPTn_CCMPA, GPTn_CCMPB, GPTn_CMPC, GPTn_CMPD, GPTn_CMPE, GPTn_CMPF, GPTn_OVF, GPTn_UDF (n=0~9). For destination signal: Only the following peripheral function are supported: ADCA0, ADCB0, ADCC0, ADCA1, ADCB1, ADCC1. |
| Module-stop function | Unsupport | |
| TrustZone Filter | Unsupport | |
| ELC delay time and interval of event request | Unsupport | In the simulator, the event requests are not lost due to the interval between event requests |
| Function | Support | Support Detail |
|---|---|---|
| General I/O Ports | Support | |
| Port Direction Control | Support | |
| Port Output Data setting | Support | |
| Pmn Output Set and Reset | Support | |
| Reflect the pin states of the port in PIDR | Support | |
| Pull-up Control | Unsupport | |
| N-Channel Open-Drain Control | Unsupport | |
| ELC_PORT control | Unsupport | |
| Port Drive Capability | Unsupport | |
| Event on Falling/Rising detection | Unsupport | |
| IRQ Input Control (When PDR=0, PMR=0, ASEL=0, ISEL=1) | Support | |
| Analog Input Control (When PDR=0, PMR=0, ASEL=1, ISEL=0) | Support | |
| Port Mode Control | Support | |
| Peripheral Select | Support | |
| Write-Protect function to PmnPFS register | Support | |
| Secure function | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
|
Request to stop output in response to detection of input level on
the corresponding GTETRGn pin (n = A to D): 1. Requests in response to setting of the POEGGn.PIDF flag (n = A to D) 2. Requests directly in response to the detected signal. |
Support Partially | Only the function (1) is supported. |
| Requests to stop output in response to detection of output stopping form GPT | Unsupport | |
| Request to stop output in response to comparator detection | Unsupport | |
| Requests to stop output by oscillation stop detection | Unsupport | |
| Requests to stop output by a register | Unsupport | |
| Interrupt | Support | |
| External trigger output to the GPT | Support | |
| Digital noise filter | Unsupport | |
| TrustZone Filter | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| 32 bits × 10 channels | Support | |
| Registers for setting up frame cycles in each channel with capability for generating interrupts at overflow or underflow | Support | |
| Generation of dead times in PWM operation | Support | |
| Synchronous starting, stopping and clearing counters for arbitrary channels | Support | |
|
Count start, count stop, count clear, up-count, down-count, or input
capture operation by the hardware sources - Up to 8 ELC event inputs - 2 input pins - Up to 4 external trigger inputs |
Unsupport | |
|
Count clock 1. GTCLK, GTCLK/2, GTCLK/4, GTCLK/8, GTCLK/16, GTCLK/32, GTCLK/64, GTCLK/128, GTCLK/256, GTCLK/512, GTCLK/1024 2. GTETRGA, GTETRGB, GTETRGC, GTETRGD |
Support Partially | Only "GTCLK" is supported. |
| External trigger input pin | Support Partially | Only output disable request from POEG is supported. |
| Counter clear sources | Support Partially | Only clearing by software source is supported. |
| Compare match output | Support | |
| Input capture function | Unsupport | |
|
PWM mode: 1. Saw-wave PWM mode 1 (single buffer or double buffer possible) 2. Saw-wave one-shot pulse mode (fixed buffer operation) 3. Saw-wave PWM mode 2 (single buffer or double buffer possible) 4. Triangle-wave PWM mode 1 (32-bit transfer at trough) 5. Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) 6. Triangle-wave PWM mode 3 (64-bit transfer at trough) 7. Complementary PWM mode 1 (transfer at crest) 8. Complementary PWM mode 2 (transfer at trough) 9. Complementary PWM mode 3 (transfer at crest and trough) 10. Complementary PWM mode 4 (immediate transfer) |
Support Partially | The single buffer of (1) and (4) are supported. |
|
Buffer operation 1. Double buffer 2. Simultaneous operation disable control for multiple channels 3. Buffer operation by counter clearing/compare match |
Support Partially | Only (3) is supported. |
| Automatic Dead Time Setting Function | Support | |
| Count Direction Changing Function | Support | |
| Period count function | Unsupport | |
| Phase count function | Unsupport | |
| External pulse width measuring function | Unsupport | |
| Logical operation between the channel output | Unsupport | |
| A/D Conversion Start Request | Support | |
|
Interrupt sources: 1. Compare match A to F event 2. overflow/underflow event 3. Compare match ADTRGA or ADTRGB event 4. Finish of period count function |
Support Partially | (1) and (2) are supported. |
| DMAC/DTC activation | Unsupport | |
| Interrupt skipping function | Unsupport | |
|
Event linking (ELC) function: 1. Compare match A to F event 2. overflow/underflow event 3. Compare match ADTRGA or ADTRGB event 4. Finish of period count function |
Support Partially | (1) and (2) are supported. |
| Noise Filter Function | Unsupport | |
| Output Phase Switching | Unsupport | |
| Output pin disable function by dead time error and detected short-circuits between output pins | Unsupport | |
| Output Protection Function for GTIOCnm Pin Output | Support |
| Function | Support | Support Detail |
|---|---|---|
|
Operating modes 1. Timer mode 2. Pulse output mode 3. Event counter mode 4. Pulse width measurement mode 5. Pulse period measurement mode |
Support Partially | Only (2) is supported. |
| Number of Channels: 32 bits × 2 channels | Support | |
|
Count source (operating clock) 1. PCLKB, PCLKB/2, PCLKB/8, AGTLCLK/d(d = 1, 2, 4, 8, 16, 32, 64, or 128), or underflow signal of AGTW0 selectable 2. External event input |
Support Partially | (1) is supported. |
|
Interrupt and Event Link function 1. Underflow event signal 2. Measurement complete event signal 3. Compare match A event signal 4. Compare match B event signal 5. Return from Snooze mode or Software Standby mode can be performed with AGT1_AGTI, AGT1_AGTCMAI, or AGT1_AGTCMBI |
Support Partially | Only (1) is supported. |
| Compare match function | Unsupport | |
| TrustZone Filter | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| Count source: IWDT-dedicated clock (IWDTCLK) | Support | |
| Clock division ratio: Division by 1, 16, 32, 64, 128, or 256 | Support | |
| Counter operation: Counting down using a 14-bit down-counter | Support | |
|
Condition for starting the counter: 1. Counting automatically starts after a reset 2. Only secure developer can start the IWDT |
Support Partially | (1) is supported. |
|
Conditions for stopping the counter 1. Reset (the down-counter and other registers return to their initial values) 2. A counter underflows or a refresh error is generated (counting restarts automatically) |
Support | |
| Window function: Window start and end positions can be specified (refresh-permitted and refresh-prohibited periods) | Support | |
|
Reset output sources: 1. Down-counter underflows 2. Refreshing outside the refresh-permitted period (refresh error) |
Support | |
|
Non-maskable interrupt/interrupt sources: 1. Down-counter underflows 2. Refreshing outside the refresh-permitted period (refresh error) |
Support | |
| Reading the counter value: The down-counter value can be read by the IWDTSR register | Support | |
| Event link function | Unsupport | |
|
Output signal (internal signal): 1. Reset output 2. Interrupt request output 3. Sleep-mode count stop control output |
Support Partially | (1) and (2) are supported. |
|
Auto start mode: 1. Clock frequency division ratio after a reset 2. Timeout period of the Independent Watchdog Timer 3. Window start position in the Independent Watchdog Timer 4. Window end position in the Independent Watchdog Timer 5. Reset output or interrupt request output 6. Down-count stop function at transition to Sleep, Snooze, or Software Standby mode |
Support Partially | (1)~(5) are supported. |
| TrustZone Filter | Unsupport |
| Function | Support | Support Detail |
|---|---|---|
| Calculation of sine, cosine, arctangent, and sqrt(x²+y²) | Support | |
| Data type for processing: Single-precision floating-point | Support | |
| Number of cycles for calculation: Sine: 14, Cosine: 14, Arctangent: 14 and √x²+y²: 14 + α | Unsupport | In the simulator, the calculation is completed immediately. |
| Function | Support | Support Detail |
|---|---|---|
| A/D converter Unit: Unit 0, Unit 1 | Support | |
|
Input channels: Up to 29 analog input channels - A/D Converter Unit 0: Up to 21 analog input channels - A/D Converter Unit 1: Up to 17 analog input channels - 9 analog input channels are shared by A/D Converter Unit 0 and Unit 1 |
Support | |
| Extended analog function | Unsupport | |
| Resolution: 12-bits | Support | |
| Conversion time and A/D conversion clock | Unsupport | |
|
Operating modes: 1. Single scan mode 2. Continuous scan mode |
Support Partially | Only (1) is supported. |
|
Conditions for A/D conversion start: 1. Software trigger 2. Trigger from Event Link Controller 3. Triggers from GPT 4. External trigger input (ADTRGn input (n=0,1)) |
Support Partially | (2) and (3) are supported. |
| Virtual Channel function (37 virtual channels) | Support | |
| Scan Group function (up to 9 scan groups) | Support | |
| Variable sampling time (select from 16 tables per virtual channel) | Unsupport | |
| Channel-dedicated sample-and-hold circuit | Support Partially | Channel-dedicated sample-and-hold processing time is not supported. |
| Self-diagnosis function for A/D Converter | Unsupport | |
| Selectable A/D-converted value addition mode or average mode | Unsupport | |
| Analog input disconnection detection assist function | Unsupport | |
| Selectable the data format from 16- / 14- / 12- / 10-bit | Support Partially | Only 12-bit data format is supported |
| Limitter Clip Function (Up to 8 tables) | Unsupport | |
| Compare Match Function (Up to 8 tables) | Unsupport | |
| Self-calibration function | Support Partially | The function and interrupt related to "Internal circuit calibration" and "Sample and Hold Calibration" are supported, but processing time for these features are not supported. |
| User's Gain adjustment function | Unsupport | |
| User's Offset adjustment function | Unsupport | |
| Built-in FIFO (8 stages per each scan group) | Unsupport | |
| Multiple A/D converters Unit-to-unit synchronous operation function | Unsupport | |
| Programmable Gain Amplifier (PGA) | Unsupport | |
|
Interrupt sources: 1. A/D scan end interrupt 2. FIFO data read request interrupt 3. FIFO data overflow interrupt 4. Limiter Clip interrupt 5. Compare Match interrupt 6. Composite Compare Match interrupt 7. A/D Converter Error interrupt 8. A/D Conversion Overflow interrupt 9. A/D Converter calibration end interrupt |
Support Partially | (1) and (9) are supported. |
| Trigger Input: Scan can be started by the trigger from the ELC | Support | |
| Event Generation | Support | |
|
Reference Voltage: - VREFH0 is the high potential reference voltage - VREFL0 is the low potential reference voltage |
Support | In the simulator, VREFH0 is 5V and VREFL0 is 0V when no voltage is input to each pin. |
| Module-stop function | Unsupport |